Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

Reza  Aditya; Robby Kurniawan Harahap

doi:10.22219/kinetik.v9i1.1808

Issue

Vol. 9, No. 1, February 2024

Issue Published : Feb 28, 2024

This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

https://doi.org/10.22219/kinetik.v9i1.1808

Reza Aditya

Gunadarma University

Robby Kurniawan Harahap

Gunadarma University

Corresponding Author(s) : Robby Kurniawan Harahap

robby_kurniawan@staff.gunadarma.ac.id

Kinetik: Game Technology, Information System, Computer Network, Computing, Electronics, and Control, Vol. 9, No. 1, February 2024
Article Published : Feb 28, 2024

Abstract

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

Keywords

Gate Diffusion Input (GDI) Technique Precharge Amplifier Power Dissipation Sense Amplifier (SA) Static Random Access Memory Transmission Gate Voltage Mode Sense Amplifier

Aditya, R. ., & Harahap, R. K. (2024). Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider. Kinetik: Game Technology, Information System, Computer Network, Computing, Electronics, and Control, 9(1), 1-8. https://doi.org/10.22219/kinetik.v9i1.1808

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References

Hansraj, A. Chaudhary, and A. Rana, “Ultra Low power SRAM Cell for High Speed Applications using 90nm CMOS Technology,” in ICRITO 2020 - IEEE 8th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions), 2020. https://doi.org/10.1109/ICRITO48877.2020.9197869
M. Devi, C. Madhu, and N. Garg, “Design and analysis of CMOS based 6T SRAM cell at different technology nodes,” in Materials Today: Proceedings, Elsevier Ltd, 2020, pp. 1695–1700. https://doi.org/10.1016/j.matpr.2020.05.130
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A. Joy and J. Kuruvilla, “A Stable Low Power Dissipating 9T SRAM For Implementation of 4x4 Memory Array with High Frequency Analysis,” 2022. https://doi.org/10.21203/rs.3.rs-436605/v1
M. Hanumanthu, K. Kavya, S. Pradeep Reddy, M. Pavan Kalyan, V. Rohitha, and N. Bala Dastagiri, “Design of SRAM Memory Using Revesible and GDI Logics,” International Journal of Advanced Trends in Engineering Science and Technology, vol. 6, no. 3, pp. 7–10, Jun. 2021. https://doi.org/10.22413/ijatest/2021/v6/i3/3
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M. Khaleqi Qaleh Jooq, A. Mir, S. Mirzakuchaki, and A. Farmani, “A robust and energy-efficient near-threshold SRAM cell utilizing ballistic carbon nanotube wrap-gate transistors,” AEU - International Journal of Electronics and Communications, vol. 110, Oct. 2019. https://doi.org/10.1016/j.aeue.2019.152874
H. Kumar and V. K. Tomar, “A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era,” Wireless Personal Communications, vol. 117, no. 3. Springer, pp. 1959–1984, Apr. 01, 2021. https://doi.org/10.1007/s11277-020-07953-4
N. Deepak and R. B. Kumar, “Certain investigations in achieving low power dissipation for SRAM cell,” Microprocess Microsyst, vol. 77, Sep. 2020. https://doi.org/10.1016/j.micpro.2020.103166
R. R. Vallabhuni, P. Shruthi, G. Kavya, and S. Siri Chandana, “6Transistor SRAM Cell designed using 18nm FinFET Technology,” in Proceedings of the 3rd International Conference on Intelligent Sustainable Systems, ICISS 2020, Institute of Electrical and Electronics Engineers Inc., Dec. 2020, pp. 1584–1589. https://doi.org/10.1109/ICISS49785.2020.9315929
M. Durga Satish and N. G. N Prasad, “Implementation of Low Area Multipliers Using Modified Gate Diffusion Input Technology.”
E. Abiri, A. Darabi, and A. Sadeghi, “Gate-diffusion input (GDI)method for designing energy-efficient circuits in analogue voltage-mode fuzzy and QCA systems,” Microelectronics J, vol. 87, pp. 81–100, May 2019. https://doi.org/10.1016/j.mejo.2019.04.001
K. Kumar, F. Noorbasha, M. Kiran Kumar, and K. S. Rao, “Design of Low Power 16X16 SRAM Array Using GDI Logic With Dynamic Threshold Technique,” vol. 12, no. 22, 2017.
T. V. Reddy and D. B. K. Madhavi, “Implementation & Comparative Analysis of CMOS vs GDI for 8T SRAM Functionality under Power, Delay over Performance,” International Journal of Advanced Engineering Research and Science, vol. 4, no. 4, pp. 171–175, 2017. https://dx.doi.org/10.22161/ijaers.4.4.24
K. Prasad Babu, N. V. Kumar, and S. Noorullah, “Article Info Page Number,” Publication Issue, vol. 71, no. 1, pp. 203–212, 2022.
C. Kishore and A. Kumar, “Comparative Analysis of Various Sense Amplifiers in 45nm CMOS Technology,” International Research Journal of Engineering and Technology, vol. 102, 2019.
IEEE Electron Devices Society. Malaysia Chapter, Universiti Putra Malaysia, International Islamic University Malaysia, and Institute of Electrical and Electronics Engineers, Proceedings of the 2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) : 21st - 23rd August 2019, Everly Hotel Putrajaya, Putrajaya, Malaysia.
D. Mittal and V. K. Tomar, “Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node,” 2020.
P. Teja and S. K. Sinha, “Power and delay analysis of different SRAM cell structures with different technology node,” Mater Today Proc, vol. 80, pp. 2285–2288, Jan. 2023. https://doi.org/10.1016/j.matpr.2021.06.232
E. Abbasian and M. Gholipour, “Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications,” AEU - International Journal of Electronics and Communications, vol. 138, Aug. 2021. https://doi.org/10.1016/j.aeue.2021.153899
U. Mushtaq and V. K. Sharma, “Design and analysis of INDEP FinFET SRAM cell at 7-nm technology,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 33, no. 5, Sep. 2020. https://doi.org/10.1002/jnm.2730
V. Choudhary and D. S. Yadav, “Analysis of Power, Delay and SNM of 6T 8T SRAM Cells,” Proceedings of the 5th International Conference on Electronics, Communication and Aerospace Technology, ICECA 2021, pp. 78–82, 2021. https://doi.org/10.1109/ICECA52323.2021.9676022
S. Naghizadeh and M. Gholami, “Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write Path,” Circuits Syst Signal Process, vol. 38, no. 1, pp. 287–303, Jan. 2019. https://doi.org/10.1007/s00034-018-0858-9
S. Saun and H. Kumar, “Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization,” IOP Conf Ser Mater Sci Eng, vol. 561, no. 1, p. 012093, Oct. 2019. https://doi.org/10.1088/1757-899X/561/1/012093
S. S. Kadam and P. Bhatasana, “Piyush Bhatasana Design Of 16-Bit Low Power SRAM In 180nm CMOS Technology,” 2022.

References

Hansraj, A. Chaudhary, and A. Rana, “Ultra Low power SRAM Cell for High Speed Applications using 90nm CMOS Technology,” in ICRITO 2020 - IEEE 8th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions), 2020. https://doi.org/10.1109/ICRITO48877.2020.9197869

M. Devi, C. Madhu, and N. Garg, “Design and analysis of CMOS based 6T SRAM cell at different technology nodes,” in Materials Today: Proceedings, Elsevier Ltd, 2020, pp. 1695–1700. https://doi.org/10.1016/j.matpr.2020.05.130

C. C. Wang, C. Y. Huang, and C. H. Yeh, “SRAM-based computation in memory architecture to realize single command of add-multiply operation and multifunction,” Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, 2021. https://doi.org/10.1109/ISCAS51556.2021.9401561

A. Joy and J. Kuruvilla, “A Stable Low Power Dissipating 9T SRAM For Implementation of 4x4 Memory Array with High Frequency Analysis,” 2022. https://doi.org/10.21203/rs.3.rs-436605/v1

M. Hanumanthu, K. Kavya, S. Pradeep Reddy, M. Pavan Kalyan, V. Rohitha, and N. Bala Dastagiri, “Design of SRAM Memory Using Revesible and GDI Logics,” International Journal of Advanced Trends in Engineering Science and Technology, vol. 6, no. 3, pp. 7–10, Jun. 2021. https://doi.org/10.22413/ijatest/2021/v6/i3/3

P. Tyagi, S. K. Singh, and P. Dua, “Gate diffusion input technique for power efficient circuits and its applications,” International Journal of Recent Technology and Engineering, vol. 8, no. 2 Special Issue 7, pp. 472–477, Jul. 2019. https://doi.org/10.35940/ijrte.B1089.0782S719

I. Rullah, R. K. Harahap, E. P. Wibowo, A. I. Sukowati, D. Nur’ainingsih, and W. Widyastuti, “Design and Simulation of Low Power and Voltage Micro Photovoltaic Cell for Mobile Devices,” Kinetik: Game Technology, Information System, Computer Network, Computing, Electronics, and Control, 2022. https://doi.org/10.22219/kinetik.v7i1.1355

M. Khaleqi Qaleh Jooq, A. Mir, S. Mirzakuchaki, and A. Farmani, “A robust and energy-efficient near-threshold SRAM cell utilizing ballistic carbon nanotube wrap-gate transistors,” AEU - International Journal of Electronics and Communications, vol. 110, Oct. 2019. https://doi.org/10.1016/j.aeue.2019.152874

H. Kumar and V. K. Tomar, “A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era,” Wireless Personal Communications, vol. 117, no. 3. Springer, pp. 1959–1984, Apr. 01, 2021. https://doi.org/10.1007/s11277-020-07953-4

N. Deepak and R. B. Kumar, “Certain investigations in achieving low power dissipation for SRAM cell,” Microprocess Microsyst, vol. 77, Sep. 2020. https://doi.org/10.1016/j.micpro.2020.103166

R. R. Vallabhuni, P. Shruthi, G. Kavya, and S. Siri Chandana, “6Transistor SRAM Cell designed using 18nm FinFET Technology,” in Proceedings of the 3rd International Conference on Intelligent Sustainable Systems, ICISS 2020, Institute of Electrical and Electronics Engineers Inc., Dec. 2020, pp. 1584–1589. https://doi.org/10.1109/ICISS49785.2020.9315929

M. Durga Satish and N. G. N Prasad, “Implementation of Low Area Multipliers Using Modified Gate Diffusion Input Technology.”

E. Abiri, A. Darabi, and A. Sadeghi, “Gate-diffusion input (GDI)method for designing energy-efficient circuits in analogue voltage-mode fuzzy and QCA systems,” Microelectronics J, vol. 87, pp. 81–100, May 2019. https://doi.org/10.1016/j.mejo.2019.04.001

K. Kumar, F. Noorbasha, M. Kiran Kumar, and K. S. Rao, “Design of Low Power 16X16 SRAM Array Using GDI Logic With Dynamic Threshold Technique,” vol. 12, no. 22, 2017.

T. V. Reddy and D. B. K. Madhavi, “Implementation & Comparative Analysis of CMOS vs GDI for 8T SRAM Functionality under Power, Delay over Performance,” International Journal of Advanced Engineering Research and Science, vol. 4, no. 4, pp. 171–175, 2017. https://dx.doi.org/10.22161/ijaers.4.4.24

K. Prasad Babu, N. V. Kumar, and S. Noorullah, “Article Info Page Number,” Publication Issue, vol. 71, no. 1, pp. 203–212, 2022.

C. Kishore and A. Kumar, “Comparative Analysis of Various Sense Amplifiers in 45nm CMOS Technology,” International Research Journal of Engineering and Technology, vol. 102, 2019.

IEEE Electron Devices Society. Malaysia Chapter, Universiti Putra Malaysia, International Islamic University Malaysia, and Institute of Electrical and Electronics Engineers, Proceedings of the 2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) : 21st - 23rd August 2019, Everly Hotel Putrajaya, Putrajaya, Malaysia.

D. Mittal and V. K. Tomar, “Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node,” 2020.

P. Teja and S. K. Sinha, “Power and delay analysis of different SRAM cell structures with different technology node,” Mater Today Proc, vol. 80, pp. 2285–2288, Jan. 2023. https://doi.org/10.1016/j.matpr.2021.06.232

E. Abbasian and M. Gholipour, “Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications,” AEU - International Journal of Electronics and Communications, vol. 138, Aug. 2021. https://doi.org/10.1016/j.aeue.2021.153899

U. Mushtaq and V. K. Sharma, “Design and analysis of INDEP FinFET SRAM cell at 7-nm technology,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 33, no. 5, Sep. 2020. https://doi.org/10.1002/jnm.2730

V. Choudhary and D. S. Yadav, “Analysis of Power, Delay and SNM of 6T 8T SRAM Cells,” Proceedings of the 5th International Conference on Electronics, Communication and Aerospace Technology, ICECA 2021, pp. 78–82, 2021. https://doi.org/10.1109/ICECA52323.2021.9676022

S. Naghizadeh and M. Gholami, “Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write Path,” Circuits Syst Signal Process, vol. 38, no. 1, pp. 287–303, Jan. 2019. https://doi.org/10.1007/s00034-018-0858-9

S. Saun and H. Kumar, “Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization,” IOP Conf Ser Mater Sci Eng, vol. 561, no. 1, p. 012093, Oct. 2019. https://doi.org/10.1088/1757-899X/561/1/012093

S. S. Kadam and P. Bhatasana, “Piyush Bhatasana Design Of 16-Bit Low Power SRAM In 180nm CMOS Technology,” 2022.

Issue

Vol. 9, No. 1, February 2024

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

Corresponding Author(s) : Robby Kurniawan Harahap

Abstract

Keywords

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References

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