Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

Widianto Widianto, Lailis Syafaah, Nurhadi Nurhadi

Abstract

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

Keywords

Process Variations, HCMOC IC, Monte Carlo, Normal Distribution

Full Text:

PDF

References

[1] K. Bernstein, et al., "High Speed CMOS Design Style", Kluwer Academic Publishers, 1999.

[2] R.C. Jaeger and T.N. Blalock, "Microelectronic Circuit Design, Fourth Edition", McGraw-Hill Companies, Inc., 2011.

[3] N.H.E. Weste and D.M. Harris, "CMOS VLSI Design, A Systems and Circuits Perspective, Fouth Edition", Addison-Wesley, 2011.

[4] M. Onabajo and J. Silva-Martinez, "Analog Circuit Design for Process Variation-Resilient System-on-a-Chip", Springer, 2012.

[5] S. Reda and S.R. Nassif, "Analzing the Impact of Process Variation on Parametic Measurements: Novel Model and Applications", Design Automation and Test in Europe, Pp. 375-380, 2009.

[6] V. Mehrotra, S.L. Sam, D. Boning, A. Chandrakasan, R. Vallishaye, and S. Nassif, "A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance", Proceedings of Design Automation Conference, Pp. 172-175, 2000.

[7] K.G. Verma and B.K. Kaushik, "Effect of Process Based Oxide Thickness Variation on the Delay of DIL System using Monte Carlo Analysis", International Journal of Recent Trends in Engineering and Technology, Vol. 3 No. 4, Pp. 28-31, 2010.

[8] M. Wirnshofer, "Variation Aware Adaptive Voltage Scaling for Digital CMOS Circuits", Springer, 2013.

[9] N. Drego, A. Chandrakasan, and D. Boning, "A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays", International Symposium on Quality Electronic Design (ISQED), Pp. 281-286, 2007.

[10] A. Beg, A. Elchouemi, and R. Beg, "Effect of Channel Lengthening and Threshold Voltage Variation on a Nanometric Gate's Delay and Power", International Conference on COmputer Design (CDES), Pp. 55-59, 2012.

[11] Widianto, Lailis Syafaah, Nurhadi, "Open Defect Detection of CMOS ICs using IDDQ Testing", National Seminar on Technology and Engineering (SENTRA), Pp. 188-190, 2016

[12] J.L. Devore, "Probability and Statistics for Engineering and the Sceiences, Eight Edition", Cengage Learning, 2012.

Refbacks

  • There are currently no refbacks.

Referencing Software:

Checked by:

Supervised by:

Statistic:

View My Stats


Creative Commons License Kinetik : Game Technology, Information System, Computer Network, Computing, Electronics, and Control by http://kinetik.umm.ac.id is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.